✦ LIBER ✦

Methodology Verification of Hierarchically Described VLSI Circuits

✍ Scribed by Bain, I.L.; Glasser, L.A.

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

Hierarchical Verification of Galois Fiel

✍ Mukhopadhyay, D.; Sengar, G.; Chowdhury, D.R. 📂 Article 📅 2007 🏛 IEEE 🌐 English ⚖ 170 KB

Simulation, synthesis, and verification

✍ Dennis Furey; Neil W. Bergmann 📂 Article 📅 1999 🏛 Elsevier Science 🌐 English ⚖ 69 KB

The halo algorithm-an algorithm for hier

✍ Hedenstierna, N.; Jeppson, K.O. 📂 Article 📅 1993 🏛 IEEE 🌐 English ⚖ 909 KB

[IEEE 7th International Conference on VL

✍ Hoskote, Y.V.; Moondanos, J.; Abraham, J.A.; Fussell, D.S. 📂 Article 📅 1994 🏛 IEEE ⚖ 431 KB

A statistical methodology for modeling a

✍ Mustapha Hamad; Sami Al-Arian; David Landis 📂 Article 📅 1997 🏛 Elsevier Science 🌐 English ⚖ 852 KB

Hierarchical Simulation of Process Varia

✍ Lorenz, J.K.; Bar, E.; Clees, T.; Jancke, R.; Salzig, C.P.J.; Selberherr, S. 📂 Article 📅 2011 🏛 IEEE 🌐 English ⚖ 315 KB