✦ LIBER ✦

Simulation, synthesis, and verification of pipelined asynchronous VLSI circuits

✍ Scribed by Dennis Furey; Neil W. Bergmann

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

Modeling and Synthesis of Asynchronous P

✍ Chong-Fatt Law; Bah-Hwee Gwee; Chang, J.S. 📂 Article 📅 2011 🏛 IEEE 🌐 English ⚖ 824 KB

Verification of asynchronous circuits ba

✍ Koichi Masukura; Minoru Tomisaka; Tomohiro Yoneda 📂 Article 📅 2001 🏛 John Wiley and Sons 🌐 English ⚖ 380 KB

CMOS VLSI circuits of pipeline sections

✍ A. Bouridane; A. Pajayakrit; S.S. Dlay; A.G.J. Holt 📂 Article 📅 1989 🏛 Elsevier Science 🌐 English ⚖ 970 KB

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✍ Zhu, Z.; Hong, W.; Chen, Y.; Wang, Y. 📂 Article 📅 1996 🏛 The Institution of Electrical Engineers 🌐 English ⚖ 571 KB

Workshop An introduction to circuit-leve

📂 Article 📅 1985 🏛 Elsevier Science 🌐 English ⚖ 68 KB

VLSI-oriented design method of asynchron

✍ Kyong-Rok Cho; Kunihiro Asada 📂 Article 📅 1992 🏛 John Wiley and Sons 🌐 English ⚖ 715 KB