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Measurements and analysis of SER-tolerant latch in a 90-nm dual-VT CMOS process

✍ Scribed by Hazucha, P.; Karnik, T.; Walstra, S.; Bloechel, B.A.; Tschanz, J.W.; Maiz, J.; Soumyanath, K.; Dermer, G.E.; Narendra, S.; De, V.; Borkar, S.

Book ID: 118058984
Publisher: IEEE
Year: 2004
Tongue: English
Weight: 891 KB
Volume: 39
Category: Article
ISSN: 0018-9200
DOI: 10.1109/jssc.2004.831449

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