Low Power Design with High-Level Power Estimation and Power-Aware Synthesis

✍ Scribed by Sumit Ahuja, Avinash Lakshminarayana, Sandeep Kumar Shukla (auth.)

• Publisher: Springer-Verlag New York
• Year: 2012
• Tongue: English
• Leaves: 193
• Edition: 1
• Category: Library

✦ Synopsis

This book presents novel research techniques, algorithms, methodologies and experimental results for high level power estimation and power aware high-level synthesis. Readers will learn to apply such techniques to enable design flows resulting in shorter time to market and successful low power ASIC/FPGA design.

✦ Table of Contents

Front Matter....Pages i-xxii
Introduction....Pages 1-12
Related Work....Pages 13-29
Background....Pages 31-43
Architectural Selection Using High Level Synthesis....Pages 45-57
Statistical Regression Based Power Models....Pages 59-70
Coprocessor Design Space Exploration Using High Level Synthesis....Pages 71-80
Regression-Based Dynamic Power Estimation for FPGAs....Pages 81-92
High Level Simulation Directed RTL Power Estimation....Pages 93-103
Applying Verification Collaterals for Accurate Power Estimation....Pages 105-118
Power Reduction Using High-Level Clock-Gating....Pages 119-129
Model-Checking to Exploit Sequential Clock-Gating....Pages 131-141
System Level Simulation Guided Approach for Clock-Gating....Pages 143-156
Conclusions....Pages 157-161
Back Matter....Pages 163-170

✦ Subjects

Circuits and Systems; Computer-Aided Engineering (CAD, CAE) and Design