Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms

✍ Scribed by Tim Kogel, Rainer Leupers, Heinrich Meyr

• Year: 2006
• Tongue: English
• Leaves: 202
• Edition: 1
• Category: Library

✦ Synopsis

Integrated System-Level Modeling of Network-on-Chip Enabled Multi-Processor Platforms first gives a comprehensive update on recent developments in the area of SoC platforms and ESL design methodologies. The main contribution is the rigorous definition of a framework for modeling at the timing approximate level of abstraction. Subsequently this book presents a set of tools for the creation and exploration of timing approximate SoC platform models.

✦ Table of Contents

Contents......Page 6
Dedication......Page 5
Foreword......Page 9
Preface......Page 11
1. INTRODUCTION......Page 13
1.1 Organization of the Book Chapters......Page 18
2.1 Networking Domain......Page 20
2.2 Multimedia Domain......Page 21
2.3 Wireless Communications......Page 22
2.4 Application Trends......Page 23
2.5 First Order Application Partitioning......Page 24
3.1 Architecture Metrics......Page 26
3.2 Processing Elements......Page 28
3.3 On-Chip Communication......Page 31
3.4 Summary......Page 41
4. SYSTEM LEVEL DESIGN PRINCIPLES......Page 44
4.1 The Platform Based Design Paradigm......Page 45
4.2 Design Phases......Page 46
4.3 Abstraction Mechanisms......Page 47
4.4 Models of Computation......Page 49
4.5 Object versus Actor Oriented Design......Page 51
4.6 System Level Design Requirements......Page 52
5.1 Traditional HW/SW Co-Design......Page 54
5.2 SystemC based Transaction Level Modeling......Page 57
5.3 Current Research on MP-SoC Design Methodologies......Page 61
5.4 Summary......Page 69
6. METHODOLOGY OVERVIEW......Page 70
6.1 Application Modeling......Page 71
6.2 Architecture Modeling......Page 75
6.3 Envisioned Design Flow......Page 80
6.4 MP-SoC Simulation Framework......Page 86
7.1 Tagged Signal Model Introduction......Page 89
7.2 Reactive Process Network......Page 95
7.3 Architecture Model......Page 102
7.4 Performance Metrics......Page 118
7.5 Summary......Page 122
8.1 The Generic Synchronization Protocol......Page 123
8.2 Generic VPU Model......Page 129
8.3 NoC Framework......Page 130
8.4 Tool Support......Page 141
8.5 Summary......Page 149
9.1 IPv4 Forwarding with QoS Support......Page 150
9.2 Intel IXP2400 Reference NPU......Page 152
9.3 Custom IPv4 Platform......Page 155
9.4 Simulation Results......Page 158
10. SUMMARY......Page 162
A The OSCI TLM Standard......Page 167
B The OCPIP TL3 Channel......Page 170
C The Architects View Framework......Page 173
List of Figures......Page 177
List of Tables......Page 180
References......Page 181
About the Authors......Page 198
D......Page 200
N......Page 201
Y......Page 202