Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms

✍ Scribed by Tim Kogel, Rainer Leupers, Heinrich Meyr (auth.)

• Publisher: Springer
• Year: 2006
• Tongue: English
• Leaves: 186
• Edition: 1
• Category: Library

✦ Synopsis

We are presently observing a paradigm change in designing complex SoC as it occurs roughly every twelve years due to the exponentially increasing number of transistors on a chip. This design discontinuity, as all previous ones, is characterized by a move to a higher level of abstraction. This is required to cope with the rapidly increasing design costs. While the present paradigm change shares the move to a higher level of abstraction with all previous ones, there exists also a key difference. For the ?rst time shrinking geometries do not leadtoacorrespondingincreaseofperformance. InarecenttalkLisaSuofIBM pointed out that in 65nm technology only about 25% of performance increase can be attributed to scaling geometries while the lion share is due to innovative processor architecture [1]. We believe that this fact will revolutionize the entire semiconductor industry. What is the reason for the end of the traditional view of Moore’s law? It is instructive to look at the major drivers of the semiconductor industry: wireless communications and multimedia. Both areas are characterized by a rapidly increasingdemandofcomputationalpowerinordertoprocessthesophisticated algorithmsnecessarytooptimallyutilizethepreciousresourcebandwidth. The computational power cannot be provided by traditional processor architectures and shared bus type of interconnects. The simple reason for this fact is energy ef?ciency: there exist orders of magnitude between the energy ef?ciency of an algorithm implemented as a ?xed functionality computational element and of a software implementation on a processor.

✦ Table of Contents

Introduction....Pages 1-7
Embedded SOC applications....Pages 9-14
Classification of platform elements....Pages 15-32
System level design principles....Pages 33-42
Related work....Pages 43-58
Methodology overview....Pages 59-77
Unified timing model....Pages 79-112
MP-SOC simulation framework....Pages 113-139
Case study....Pages 141-152
Summary....Pages 153-157

✦ Subjects

Computer-Aided Engineering (CAD, CAE