๐”– Scriptorium
โœฆ   LIBER   โœฆ
๐Ÿ“

High-level estimation and exploration of reliability for multi-processor system-on-chip

โœ Scribed by Chattopadhyay, Anupam; Wang, Zheng

Publisher
Springer
Year
2018
Tongue
English
Leaves
210
Series
Computer architecture and design methodologies
Category
Library
โฌ‡  Acquire This Volume

No coin nor oath required. For personal study only.

โœฆ Synopsis

This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of Read more...


Abstract: This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures

โœฆ Table of Contents

Front Matter....Pages i-xx
Introduction....Pages 1-4
Background....Pages 5-10
State-of-the-Art....Pages 11-28
High-Level Fault Injection and Simulation....Pages 29-80
Architectural Reliability Estimation....Pages 81-117
Architectural Reliability Exploration....Pages 119-153
System-Level Reliability Exploration....Pages 155-176
Conclusion and Outlook....Pages 177-179
Back Matter....Pages 181-197

โœฆ Subjects

Systems on a chip;Fault-tolerant computing;COMPUTERS / General

๐Ÿ“œ SIMILAR VOLUMES

Integrated System-Level Modeling of Netw
๐Ÿ“ Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms
โœ Tim Kogel, Rainer Leupers, Heinrich Meyr ๐Ÿ“‚ Library ๐Ÿ“… 2006 ๐ŸŒ English

Integrated System-Level Modeling of Network-on-Chip Enabled Multi-Processor Platforms first gives a comprehensive update on recent developments in the area of SoC platforms and ESL design methodologies. The main contribution is the rigorous definition of a framework for modeling at the timing approx

Integrated System-Level Modeling of Netw
๐Ÿ“ Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms
โœ Tim Kogel, Rainer Leupers, Heinrich Meyr (auth.) ๐Ÿ“‚ Library ๐Ÿ“… 2006 ๐Ÿ› Springer ๐ŸŒ English

<p>We are presently observing a paradigm change in designing complex SoC as it occurs roughly every twelve years due to the exponentially increasing number of transistors on a chip. This design discontinuity, as all previous ones, is characterized by a move to a higher level of abstraction. This is

Multi-Processor System-on-Chip 2
๐Ÿ“ Multi-Processor System-on-Chip 2
โœ Liliana Andrade, Frederic Rousseau ๐Ÿ“‚ Library ๐Ÿ“… 2021 ๐ŸŒ English

A Multi-Processor System-on-Chip (MPSoC) is the key component for complex applications. These applications put huge pressure on memory, communication devices and computing units. This book, presented in two volumes โ€“ Architectures and Applications โ€“ therefore celebrates the 20th anniversary of MPSoC