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Influence of well profile and gate length on the ESD performance of a fully silicided 0.25 μm CMOS technology

✍ Scribed by Bock, K.; Russ, C.; Badenes, G.; Groeseneken, G.; Deferm, L.

Book ID: 114560669
Publisher: IEEE
Year: 1998
Weight: 272 KB
Volume: 21
Category: Article
ISSN: 1083-4400
DOI: 10.1109/3476.739173

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