✦ LIBER ✦

Inclusion-exclusion principle in the design of a BIST unit for LSI and VLSI circuits

✍ Scribed by I. P. Kobyak

Book ID: 110214243
Publisher: Springer
Year: 2006
Tongue: English
Weight: 220 KB
Volume: 35
Category: Article
ISSN: 1063-7397
DOI: 10.1134/s1063739706020089

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

SPIE Proceedings [SPIE Microtechnologies

SPIE Proceedings [SPIE Microtechnologies for the New Millennium 2005 - Sevilla, Spain (Monday 9 May 2005)] VLSI Circuits and Systems II - Digital test of a ΣΔ modulator in a mixed-signal BIST architecture

✍ Rolindez, Luis; Mir, Salvador; Prenat, Guillaume; Lopez, Jose F.; Fernandez, Fra 📂 Article 📅 2005 🏛 SPIE ⚖ 545 KB

[Lecture Notes in Computer Science] Prog

[Lecture Notes in Computer Science] Progress in VLSI Design and Test Volume 7373 || Implementation of a New Offset Generator Block for the Low-Voltage, Low-Power Self Biased Threshold Voltage Extractor Circuit

✍ Rahaman, Hafizur; Chattopadhyay, Sanatan; Chattopadhyay, Santanu 📂 Article 📅 2012 🏛 Springer Berlin Heidelberg 🌐 English ⚖ 297 KB

This book constitutes the refereed proceedings of the 16th International Symposium on VSLI Design and Test, VDAT 2012, held in Shibpur, India, in July 2012. The 30 revised regular papers presented together with 10 short papers and 13 poster sessions were carefully selected from 135 submissions. The

[IEEE 1997 IEEE International Symposium

[IEEE 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97 - Hong Kong (9-12 June 1997)] Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97 - A new true-single-phase-clocked double-edge-triggered flip-flop for low-power VLSI designs

✍ Jinn-Shyan Wang, 📂 Article 📅 1997 🏛 IEEE ⚖ 322 KB

[IEEE 2013 International Conference on T

[IEEE 2013 International Conference on Technological Advances in Electrical, Electronics and Computer Engineering (TAEECE) - Konya, Turkey (2013.05.9-2013.05.11)] 2013 The International Conference on Technological Advances in Electrical, Electronics and Computer Engineering (TAEECE) - A unique technique for reducing the effects of hot-carrier induced degradations in CMOS bistable circuits for fault tolerant VLSI design

✍ Das, A.G.M. 📂 Article 📅 2013 🏛 IEEE ⚖ 588 KB