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[IEEE IEEE International Electron Devices Meeting 2003 - Washington, DC, USA (8-10 Dec. 2003)] IEEE International Electron Devices Meeting 2003 - A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors

✍ Scribed by Ghani, T.; Armstrong, M.; Auth, C.; Bost, M.; Charvat, P.; Glass, G.; Hoffmann, T.; Johnson, K.; Kenyon, C.; Klaus, J.; McIntyre, B.; Mistry, K.; Murthy, A.; Sandford, J.; Silberstein, M.; Sivakumar, S.; Smith, P.; Zawadzki, K.; Thompson, S.; Bohr, M.

Book ID: 111876363
Publisher: IEEE
Year: 2003
Weight: 214 KB
Edition: 1
Volume: 0
Category: Article
ISBN-13: 9780780378728
DOI: 10.1109/iedm.2003.1269442

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