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[IEEE ESSDERC 2003. 33rd European Solid-State Device Research - ESSDERC '03 - Estoril, Portugal (16-18 Sept. 2003)] Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710) - From feature scale simulation to backend simulation for a 100 nm CMOS process

✍ Scribed by Badrieh, F.; Puchner, H.; Heitzinger, C.; Sheikholesiami, A.; Selberherr, S.

Book ID: 126757317
Publisher: IEEE
Year: 2003
Weight: 371 KB
Category: Article
ISBN-13: 9780780379992
DOI: 10.1109/ESSDERC.2003.1256908

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