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[IEEE Digest of Technical Papers., 1990 Symposium on VLSI Circuits - Honolulu, Hawaii, USA (1990.06.7-1990.06.9)] Digest of Technical Papers., 1990 Symposium on VLSI Circuits - A 140-MHz CMOS bit-level pipelined multiplier-accumulator using a new dynamic full-adder cell design

✍ Scribed by Lu, F.; Samueli, H.

Book ID: 126818351
Publisher: IEEE
Year: 1990
Weight: 237 KB
Category: Article
DOI: 10.1109/vlsic.1990.111126

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