[IEEE Comput. Soc Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. NO.97TB100159) - San Jose, CA, USA (11-12 Aug. 1997)] Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. NO.97TB100159) - A product development flow with metrics for memory designs

[IEEE Comput. Soc International Workshop

[IEEE Comput. Soc International Workshop on Memory Technology, Design and Testing - San Jose, CA, USA (24-25 Aug. 1998)] Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. No.98TB100236) - Integration of non-classical faults in standard March tests

✍ Niggemeyer, D.; Redeker, M.; Otterstedt, J. 📂 Article 📅 1998 🏛 IEEE Comput. Soc ⚖ 42 KB

[IEEE Comput. Soc. Press IEEE Internatio

[IEEE Comput. Soc. Press IEEE International Workshop on Memory Technology, Design, and Test - San Jose, CA, USA (8-9 Aug. 1994)] Proceedings of IEEE International Workshop on Memory Technology, Design, and Test - Design of an active memory system for network applications

✍ Asthana, A.; Cravatts, M.; Krzyzanowski, P. 📂 Article 📅 1994 🏛 IEEE Comput. Soc. Press ⚖ 611 KB

[IEEE Comput. Soc 2001 IEEE Internationa

[IEEE Comput. Soc 2001 IEEE International Workshop on Memory Technology, Design and Testing - San Jose, CA, USA (6-7 Aug. 2001)] Proceedings 2001 IEEE International Workshop on Memory Technology, Design and Testing - Low output resistance charge pump for flash memory programming

✍ Khouri, S.; Gregori, S.; Micheloni, R.; Soltesz, D.; Torelli, G. 📂 Article 📅 2001 🏛 IEEE Comput. Soc 🌐 English ⚖ 436 KB

The 14 papers in this collection from the August 2001 workshop are divided into five sessions on semiconductor memory design, BIST, redundancy and error control, fault models and multi-port SRAM testing, and verification and testing. Some of the topics are evaluation of redundancy analysis algorithm

[IEEE Comput. Soc 2001 IEEE Internationa

[IEEE Comput. Soc 2001 IEEE International Workshop on Memory Technology, Design and Testing - San Jose, CA, USA (6-7 Aug. 2001)] Proceedings 2001 IEEE International Workshop on Memory Technology, Design and Testing - An error control code scheme for multilevel Flash memories

✍ Gregori, S.; Khouri, O.; Micheloni, R.; Torelli, G. 📂 Article 📅 2001 🏛 IEEE Comput. Soc 🌐 English ⚖ 365 KB

The 14 papers in this collection from the August 2001 workshop are divided into five sessions on semiconductor memory design, BIST, redundancy and error control, fault models and multi-port SRAM testing, and verification and testing. Some of the topics are evaluation of redundancy analysis algorithm

[IEEE Comput. Soc 2001 IEEE Internationa

[IEEE Comput. Soc 2001 IEEE International Workshop on Memory Technology, Design and Testing - San Jose, CA, USA (6-7 Aug. 2001)] Proceedings 2001 IEEE International Workshop on Memory Technology, Design and Testing - A parallel approach for testing multi-port static random access memories

✍ Karimi, F.; Irrinki, S.; Crosbuy, T.; Lombardi, F. 📂 Article 📅 2001 🏛 IEEE Comput. Soc 🌐 English ⚖ 680 KB

The 14 papers in this collection from the August 2001 workshop are divided into five sessions on semiconductor memory design, BIST, redundancy and error control, fault models and multi-port SRAM testing, and verification and testing. Some of the topics are evaluation of redundancy analysis algorithm

[IEEE Comput. Soc. Press IEEE Internatio

[IEEE Comput. Soc. Press IEEE International Workshop on Memory Technology, Design, and Test - San Jose, CA, USA (8-9 Aug. 1994)] Proceedings of IEEE International Workshop on Memory Technology, Design, and Test - Using sinusoidal stimuli and Fourier analyses for memory IC testing

✍ Thibeault, C. 📂 Article 📅 1994 🏛 IEEE Comput. Soc. Press ⚖ 470 KB