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[IEEE Comput. Soc Proceedings. 34th International Symposium on Multiple-Valued Logic - Toronto, Ont., Canada (19-22 May 2004)] Proceedings. 34th International Symposium on Multiple-Valued Logic - Design of quaternary logic gate using double pass-transistor logic with neuron MOS down literal circuit

✍ Scribed by Soo Jin Park, ; Byoung Hee Yoon, ; Kwang Sub Yoon, ; Heung Soo Kim,

Book ID: 120690760
Publisher: IEEE Comput. Soc
Year: 2004
Weight: 352 KB
Category: Article
ISBN-13: 9780769521305
DOI: 10.1109/ISMVL.2004.1319941

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