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[IEEE Comput. Soc Proceedings. 34th International Symposium on Multiple-Valued Logic - Toronto, Ont., Canada (19-22 May 2004)] Proceedings. 34th International Symposium on Multiple-Valued Logic - A single-electron-transistor logic gate family and its application - Part II: design and simulation of a 7-3 parallel counter with linear summation and multiple-valued latch functions

✍ Scribed by Inokawa, H.; Takahashi, Y.

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