𝔖 Bobbio Scriptorium

✦ LIBER ✦

[IEEE Comput. Soc IEEE European Test Workshop - Cascais, Portugal (23-26 May 2000)] Proceedings IEEE European Test Workshop - Combining symbolic and genetic techniques for efficient sequential circuit test generation

✍ Scribed by Boschini, M.; Yu, X.; Fummi, F.; Rudnick, E.M.

Book ID: 126018395
Publisher: IEEE Comput. Soc
Year: 2000
Weight: 738 KB
Edition: 2000
Category: Article
ISBN-13: 9780769507019
DOI: 10.1109/ETW.2000.873786

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

[IEEE Comput. Soc IEEE European Test Wor

[IEEE Comput. Soc IEEE European Test Workshop - Cascais, Portugal (23-26 May 2000)] Proceedings IEEE European Test Workshop - CA-CSTP: a new BIST architecture for sequential circuits

✍ Corno, F.; Sonza Reorda, M.; Squillero, G.; Violante, M. 📂 Article 📅 2000 🏛 IEEE Comput. Soc ⚖ 410 KB

[IEEE Comput. Soc IEEE European Test Wor

[IEEE Comput. Soc IEEE European Test Workshop - Cascais, Portugal (23-26 May 2000)] Proceedings IEEE European Test Workshop - How to avoid random walks in hierarchical test path identification

✍ Makris, Y.; Collins, J.; Orailoglu, A. 📂 Article 📅 2000 🏛 IEEE Comput. Soc ⚖ 782 KB

[IEEE Comput. Soc IEEE European Test Wor

[IEEE Comput. Soc IEEE European Test Workshop - Cascais, Portugal (23-26 May 2000)] Proceedings IEEE European Test Workshop - Compressed bit fail maps for memory fail pattern classification

✍ Vollrath, J.; Lederer, U.; Hladschik, T. 📂 Article 📅 2000 🏛 IEEE Comput. Soc ⚖ 491 KB

[IEEE Comput. Soc IEEE European Test Wor

[IEEE Comput. Soc IEEE European Test Workshop - Cascais, Portugal (23-26 May 2000)] Proceedings IEEE European Test Workshop - Fast and low-area TPGs based on T-type flip-flops can be easily integrated to the scan path

✍ Garbolino, T.; Hlawiczka, A.; Kristof, A. 📂 Article 📅 2000 🏛 IEEE Comput. Soc ⚖ 551 KB

[IEEE Comput. Soc 8th IEEE European Test

[IEEE Comput. Soc 8th IEEE European Test Workshop (ETW 03) - Maastricht, Netherlands (25-28 May 2003)] The Eighth IEEE European Test Workshop, 2003. Proceedings. - Automatic worst case pattern generation using neural networks & genetic algorithm for estimation of switching noise on power supply lines in CMOS circuits

✍ Liau, E.; Schmitt-Landsiedel, D. 📂 Article 📅 2003 🏛 IEEE Comput. Soc ⚖ 224 KB