[IEEE Comput. Soc 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - San Francisco, CA, USA (24-26 Oct. 2001)] Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Comparison and application of different VHDL-based fault injection techniques

[IEEE Comput. Soc 2001 IEEE Internationa

[IEEE Comput. Soc 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - San Francisco, CA, USA (24-26 Oct. 2001)] Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Fast run-time fault location in dependable FPGA-based applications

✍ Wei-Je Huang, ; Mitra, S.; McCluskey, E.J. 📂 Article 📅 2001 🏛 IEEE Comput. Soc 🌐 English ⚖ 156 KB

Taken from the October 2001 San Francisco conference, 55 papers discuss water scale, yield, dependable design, testing techniques, fault-tolerance in arrays, fault detection, FPGA based applications, fault injection, error correcting codes, mixed signal circuits, defect analysis, self-checking and f

[IEEE Comput. Soc 2001 IEEE Internationa

[IEEE Comput. Soc 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - San Francisco, CA, USA (24-26 Oct. 2001)] Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - A step response based mixed-signal BIST approach

✍ Walker, A. 📂 Article 📅 2001 🏛 IEEE Comput. Soc 🌐 English ⚖ 223 KB

Taken from the October 2001 San Francisco conference, 55 papers discuss water scale, yield, dependable design, testing techniques, fault-tolerance in arrays, fault detection, FPGA based applications, fault injection, error correcting codes, mixed signal circuits, defect analysis, self-checking and f

[IEEE Comput. Soc 2001 IEEE Internationa

[IEEE Comput. Soc 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - San Francisco, CA, USA (24-26 Oct. 2001)] Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - On-line error detectable carry-free adder design

✍ Lala, P.K.; Walker, A. 📂 Article 📅 2001 🏛 IEEE Comput. Soc 🌐 English ⚖ 121 KB

Taken from the October 2001 San Francisco conference, 55 papers discuss water scale, yield, dependable design, testing techniques, fault-tolerance in arrays, fault detection, FPGA based applications, fault injection, error correcting codes, mixed signal circuits, defect analysis, self-checking and f

[IEEE Comput. Soc 2001 IEEE Internationa

[IEEE Comput. Soc 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - San Francisco, CA, USA (24-26 Oct. 2001)] Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - A simple via duplication tool for yield enhancement

✍ Harrison, N. 📂 Article 📅 2001 🏛 IEEE Comput. Soc 🌐 English ⚖ 241 KB

Taken from the October 2001 San Francisco conference, 55 papers discuss water scale, yield, dependable design, testing techniques, fault-tolerance in arrays, fault detection, FPGA based applications, fault injection, error correcting codes, mixed signal circuits, defect analysis, self-checking and f

[IEEE Comput. Soc 2001 IEEE Internationa

[IEEE Comput. Soc 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - San Francisco, CA, USA (24-26 Oct. 2001)] Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Enhanced concurrent error correcting arithmetic unit design using alternating logic

✍ Tat Ngai, ; Chen He, ; Swartzlander, E.E.Jr. 📂 Article 📅 2001 🏛 IEEE Comput. Soc 🌐 English ⚖ 116 KB

Taken from the October 2001 San Francisco conference, 55 papers discuss water scale, yield, dependable design, testing techniques, fault-tolerance in arrays, fault detection, FPGA based applications, fault injection, error correcting codes, mixed signal circuits, defect analysis, self-checking and f

[IEEE Comput. Soc 2001 IEEE Internationa

[IEEE Comput. Soc 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - San Francisco, CA, USA (24-26 Oct. 2001)] Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Development of the special software tools for the defect/fault analysis in the complex gates from standard cell library

✍ Blyzniuk, M.; Kazymyra, I. 📂 Article 📅 2001 🏛 IEEE Comput. Soc ⚖ 538 KB