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[IEEE Comput. Soc 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Boston, MA, USA (3-5 Nov. 2003)] Proceedings. 16th IEEE Symposium on Computer Arithmetic - Fault tolerant design of combinational and sequential logic based on a parity check code

✍ Scribed by Almukhaizim, S.; Makris, Y.

Book ID: 124077821
Publisher: IEEE Comput. Soc
Year: 2003
Weight: 259 KB
Category: Article
ISBN-13: 9780769520421
DOI: 10.1109/DFTVS.2003.1250156

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