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[IEEE Comput. Soc 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Boston, MA, USA (3-5 Nov. 2003)] Proceedings. 16th IEEE Symposium on Computer Arithmetic - Hybrid BIST time minimization for core-based systems with STUMPS architecture

✍ Scribed by Jervan, G.; Eles, P.; Peng, Z.; Ubar, R.; Jenihhin, M.

Book ID: 120249580
Publisher: IEEE Comput. Soc
Year: 2003
Weight: 233 KB
Category: Article
ISBN-13: 9780769520421
DOI: 10.1109/DFTVS.2003.1250116

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