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[IEEE 2014 IEEE Symposium on VLSI Technology - Honolulu, HI, USA (2014.6.9-2014.6.12)] 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers - Design methodology of tri-gate poly-Si MOSFETs with 10nm nanowire channel to enhance short-channel performance and reduce Vth & Id variability

✍ Scribed by Saitoh, Masumi; Ota, Kensuke; Tanaka, Chika; Numata, Toshinori

Book ID: 127001267
Publisher: IEEE
Year: 2014
Weight: 432 KB
Category: Article
ISBN: 1479933309
DOI: 10.1109/vlsit.2014.6894425

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