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[IEEE 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) - Karlovy Vary (2013.4.8-2013.4.10)] 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) - Area-speed efficient modular architecture for GF(2m) multipliers dedicated for cryptographic applications

✍ Scribed by Pamula, D.; Hrynkiewicz, E.

Book ID: 120573527
Publisher: IEEE
Year: 2013
Weight: 219 KB
Category: Article
ISBN: 1467361348
DOI: 10.1109/DDECS.2013.6549784

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