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[IEEE 2012 IEEE International Solid- State Circuits Conference - (ISSCC) - San Francisco, CA, USA (2012.02.19-2012.02.23)] 2012 IEEE International Solid-State Circuits Conference - A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and ×4 half-page architecture

✍ Scribed by Koo, Kibong; Ok, Sunghwa; Kang, Yonggu; Kim, Seungbong; Song, Choungki; Lee, Hyeyoung; Kim, Hyungsoo; Kim, Yongmi; Lee, Jeonghun; Oak, Seunghan; Lee, Yosep; Lee, Jungyu; Lee, Joongho; Lee, Hyungyu; Jang, Jaemin; Jung, Jongho; Choi, Byeongchan; Kim, Yongju; Hur, Youngdo; Kim, Yunsaing; Chung, Byongtae; Kim, Yongtak

Book ID: 111876955
Publisher: IEEE
Year: 2012
Weight: 304 KB
Volume: 0
Category: Article
ISBN: 1467303755
DOI: 10.1109/isscc.2012.6176869

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