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[IEEE 2012 IEEE International Solid- State Circuits Conference - (ISSCC) - San Francisco, CA, USA (2012.02.19-2012.02.23)] 2012 IEEE International Solid-State Circuits Conference - A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme

✍ Scribed by Sohn, Kyomin; Na, Taesik; Song, Indal; Shim, Yong; Bae, Wonil; Kang, Sanghee; Lee, Dongsu; Jung, Hangyun; Jeoung, Hanki; Lee, Ki-Won; Park, Junsuk; Lee, Jongeun; Lee, Byunghyun; Jun, Inwoo; Park, Juseop; Park, Junghwan; Choi, Hundai; Kim, Sanghee; Chung, Haeyoung; Choi, Young; Jung, Dae-Hee; Choi, Jang Seok; Moon, Byungsick; Choi, Jung-Hwan; Kim, Byungchul; Jang, Seong-Jin; Choi, Joo Sun; Oh, Kyung Seok

Book ID: 111876954
Publisher: IEEE
Year: 2012
Weight: 326 KB
Volume: 0
Category: Article
ISBN: 1467303755
DOI: 10.1109/isscc.2012.6176868

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