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[IEEE 2011 IEEE 20th Asian Test Symposium (ATS) - New Delhi, India (2011.11.20-2011.11.23)] 2011 Asian Test Symposium - A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits

✍ Scribed by Tran, D.A.; Virazel, A.; Bosio, A.; Dilillo, L.; Girard, P.; Pravossoudovitch, S.; Wunderlich, H.-J.

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