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[IEEE 2010 International Symposium on VLSI Design, Automation and Test (VLSI-DAT 2010) - Hsin Chu (2010.04.26-2010.04.29)] Proceedings of 2010 International Symposium on VLSI Design, Automation and Test - Cache-aware task scheduling on multi-core architecture

✍ Scribed by Teng-Feng Yang, ; Chung-Hsiang Lin, ; Chia-Lin Yang,

Book ID: 120235644
Publisher: IEEE
Year: 2010
Weight: 234 KB
Category: Article
ISBN: 1424452694
DOI: 10.1109/VDAT.2010.5496710

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