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[IEEE 2008 International Solid-State Circuits Conference - (ISSCC) - San Francisco, CA, USA (2008.02.3-2008.02.7)] 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers - A 45nm 4Gb 3-Dimensional Double-Stacked Multi-Level NAND Flash Memory with Shared Bitline Structure

✍ Scribed by Park, Ki-Tae; Kim, Doogon; Hwang, Soonwook; Kang, Myounggon; Cho, Hoosung; Jeong, Youngwook; Seo, Yong-Il; Jang, Jaehoon; Kim, Han-Soo; Jung, Soon-Moon; Lee, Yeong-Taek; Kim, Changhyun; Lee, Won-Seong

Book ID: 111938807
Publisher: IEEE
Year: 2008
Weight: 434 KB
Volume: 0
Category: Article
ISBN: 1424420113
DOI: 10.1109/isscc.2008.4523281

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