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Hierarchical test generation and design for testability methods for ASPPs and ASIPs

✍ Scribed by Ghosh, I.; Raghunathan, A.; Jha, N.K.


Book ID
119778436
Publisher
IEEE
Year
1999
Tongue
English
Weight
361 KB
Volume
18
Category
Article
ISSN
0278-0070

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Combined probabilistic testability calcu
✍ BjΓΈrg Reppen; Einar J. Aas πŸ“‚ Article πŸ“… 1991 πŸ› Springer US 🌐 English βš– 1017 KB

PLAs (programmable logic arrays) may be tested internally by self-test, or externally by applying test patterns. Fault coverage by nonexhaustive self-test is assured by computing a lower bound for estimated fault coverage vs. test pattern number. First, a lower bound for probabilistic detectability