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Hierarchical redundancy for array-structure wsis

✍ Scribed by Nobuo Tsuda

Book ID
104591587
Publisher
John Wiley and Sons
Year
1993
Tongue
English
Weight
1020 KB
Volume
24
Category
Article
ISSN
0882-1666

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✦ Synopsis

Abstract

This paper proposes hierarchical redundancy configurations for defect tolerance of large‐area monolithic LSIs (wafer‐scale integrated circuits or WSIs) with array structures. It also specifies how much the integration scales can be increased by expanding hierarchical levels, based on four kinds of one‐dimensional/two‐dimensional array‐connection models. Hierarchical redundancy helps to extend the defect tolerance coverage to additional replacement circuits while maintaining a high level of spare effectiveness. An estimate based on the evaluation of nonredundant additional replacement‐circuit scales indicates that four‐level hierarchical redundancy configurations can increase integration scales by a factor of 64 to 1024 compared to nonredundant LSIs.

📜 SIMILAR VOLUMES

Hierarchical redundancy for two-dimensio
Hierarchical redundancy for two-dimensional orthogonal arrays using defect-tolerant replacement circuits
✍ Nobuo Tsuda 📂 Article 📅 1993 🏛 John Wiley and Sons 🌐 English ⚖ 847 KB

## Abstract Hierarchical redundancy using defect‐tolerant replacement circuits is proposed as a means to increase the yield of large‐area LSIs (WSIs) with mesh‐connected array structures. The defect‐tolerant replacement circuits can be constructed by using direct‐connection paths and distributed sw