๐”– Bobbio Scriptorium
โœฆ   LIBER   โœฆ

A parallel reconfiguration algorithm for WSI/VLSI processor arrays

โœ Scribed by Jung H Kim; Kemal Efe


Publisher
Elsevier Science
Year
1993
Tongue
English
Weight
886 KB
Volume
17
Category
Article
ISSN
0141-9331

No coin nor oath required. For personal study only.


๐Ÿ“œ SIMILAR VOLUMES


Design of a WSI scale parallel processor
โœ Yoshichika Fujioka; Nobuhiro Tomabechi ๐Ÿ“‚ Article ๐Ÿ“… 2000 ๐Ÿ› John Wiley and Sons ๐ŸŒ English โš– 254 KB ๐Ÿ‘ 1 views

A restructurable (reconfigurable) parallel VLSI processor designed to minimize the operation delay time which can be generally used for various operations necessary for controlling an intelligent robot was proposed previously by the authors. This processor is constructed by connecting a number of pr