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Graph-theoretic algorithm for finding maximal supergates in combinational logic circuits

โœ Scribed by Min, H.B.; Park, E.S.

Book ID
114447545
Publisher
The Institution of Electrical Engineers
Year
1996
Tongue
English
Weight
662 KB
Volume
143
Category
Article
ISSN
1350-2409

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A new algorithm to generate test sets for stuck-at faults in combinational logic circuits via fault simulation is presented. The algorithm is non-path-sensitizing, non-pathtracing and can be easily implemented on a computer. The stuck-at fault model in the algorithm is developed using the component