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Gate Sizing for Cell-Library-Based Designs

โœ Scribed by Shiyan Hu; Ketkar, M.; Jiang Hu


Book ID
117908225
Publisher
IEEE
Year
2009
Tongue
English
Weight
410 KB
Volume
28
Category
Article
ISSN
0278-0070

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This paper presents a methodology for designing primitive gates in a CMOS standard cell library. The topological design space of the gates is restricted to varying the p-to n-fet width ratio and the optimal ratio is determined analytically. With topology thus "xed, gate size selection is performed a