✦ LIBER ✦

Estimation of Test Metrics for the Optimisation of Analogue Circuit Testing

✍ Scribed by Ahcène Bounceur; Salvador Mir; Emmanuel Simeu; Luis Rolíndez

Book ID: 106384332
Publisher: Springer US
Year: 2007
Tongue: English
Weight: 649 KB
Volume: 23
Category: Article
ISSN: 0923-8174
DOI: 10.1007/s10836-007-5006-6

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

Generation of optimised fault lists for

Generation of optimised fault lists for simulation of analogue circuits and test programs

✍ Milne, A.; Taylor, D.; Saunders, J.; Talbot, A.D. 📂 Article 📅 1999 🏛 The Institution of Electrical Engineers 🌐 English ⚖ 404 KB

Application of Supply Current Testing to

Application of Supply Current Testing to Analogue Circuits, Towards a Structural Analogue Test Methodology

✍ H. Manhaeve; J. Verfaillie; B. Straka; J.P. Cornil 📂 Article 📅 2000 🏛 Springer US 🌐 English ⚖ 143 KB

Estimation of Analog Parametric Test Met

Estimation of Analog Parametric Test Metrics Using Copulas

✍ Bounceur, A.; Mir, S.; Stratigopoulos, H.-G. 📂 Article 📅 2011 🏛 IEEE 🌐 English ⚖ 940 KB

Thermal Testing of Analogue Integrated C

Thermal Testing of Analogue Integrated Circuits: A Case Study

✍ J. Altet; A. Ivanov; A. Wong 📂 Article 📅 2003 🏛 Springer US 🌐 English ⚖ 255 KB

Design of testing circuit and test gener

Design of testing circuit and test generation for built-in current testing

✍ Yukiya Miura; Yasushi Wada; Kozo Kinoshita 📂 Article 📅 1993 🏛 John Wiley and Sons 🌐 English ⚖ 736 KB

## Abstract Recently current testing is beginning to be noticed as a testing method for CMOS circuits. However, since CMOS circuits cause the dynamic current due to switching, it has been pointed out that testing at a fast clock rate by current testing is difficult. To cope with this problem a buil

A metric for estimating the fault-secure

A metric for estimating the fault-secure behavior of digital circuits

✍ McNamer, M.; Kanopoulos, N. 📂 Article 📅 1998 🏛 IEEE 🌐 English ⚖ 762 KB