✦ LIBER ✦

ECL gate arrays ‘have 0.5 ns delay’

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

An ECL 5000-gate gate array with 190-ps

✍ Tatsuki, M.; Kato, S.; Okabe, M.; Yakushiji, H.; Kuramitsu, Y. 📂 Article 📅 1986 🏛 IEEE 🌐 English ⚖ 920 KB

A 1.0-ns 5-kbit ECL RAM

✍ Chuang, G.; Tang, D.D.; Li, G.P.; Hackbarth, E.; Boedeker, R.R. 📂 Article 📅 1986 🏛 IEEE 🌐 English ⚖ 729 KB

Advanced 5K-gate bipolar gate array with

✍ Suzuki, M.; Okamoto, H.; Horiguchi, S. 📂 Article 📅 1984 🏛 IEEE 🌐 English ⚖ 296 KB

Logic arrays in HCMOS have 1k gate equiv

📂 Article 📅 1984 🏛 Elsevier Science 🌐 English ⚖ 109 KB

A 6.5-ns GaAs 20×20-b parallel multiplie

✍ Singh, H.P.; Burrier, R.A.; Sadler, R.A. 📂 Article 📅 1990 🏛 IEEE 🌐 English ⚖ 602 KB

0.5-μm 2 M-transistor BiPNMOS channelles

✍ Hara, H.; Sakurai, T.; Noda, M.; Nagamatsu, T.; Seta, K.; Momose, H.; Niitsu, Y. 📂 Article 📅 1991 🏛 IEEE 🌐 English ⚖ 685 KB