New design method for tapered buffer cir
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Shigeyoshi Watanabe
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Article
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2004
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John Wiley and Sons
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English
β 682 KB
## Abstract A new design method has been conceived for a buffer circuit using TIS. In the buffer circuit of a taper type with a fanβout of 3 intended for driving a large load capacitance, a new design procedure is conceived that minimizes the pattern area without sacrificing characteristics such as