New design method for tapered buffer circuit with TIS (Trench-Isolated Transistor using sidewall gate) and its application to high-density DRAMs
✍ Scribed by Shigeyoshi Watanabe
- Book ID
- 102822645
- Publisher
- John Wiley and Sons
- Year
- 2004
- Tongue
- English
- Weight
- 682 KB
- Volume
- 87
- Category
- Article
- ISSN
- 8756-663X
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✦ Synopsis
Abstract
A new design method has been conceived for a buffer circuit using TIS. In the buffer circuit of a taper type with a fan‐out of 3 intended for driving a large load capacitance, a new design procedure is conceived that minimizes the pattern area without sacrificing characteristics such as power consumption. In the new design method, the “planar+TIS” method is employed, in which planar‐type transistors are used in the front stage of the buffer circuit while TIS‐type transistors are used in the latter stage. This design method is applied to a large‐capacity DRAM. Relative to the case in which conventional planar transistors are used, the chip area can be reduced by about 8% without sacrificing characteristics such as power consumption. © 2004 Wiley Periodicals, Inc. Electron Comm Jpn Pt 2, 87(4): 9–15, 2004; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjb.10152