✦ LIBER ✦

Device and Architecture Cooptimization for FPGA Power Reduction

✍ Scribed by Lerong Cheng; Fei Li; Yan Lin; Wong, P.; Lei He

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

Power Measurement Methodology for FPGA D

✍ Jevtic, R.; Carreras, C. 📂 Article 📅 2011 🏛 IEEE 🌐 English ⚖ 825 KB

Field Programmability of Supply Voltages

✍ Fei Li; Lin, Y.; Lei He 📂 Article 📅 2007 🏛 IEEE 🌐 English ⚖ 842 KB

Input Vector Reordering for Leakage Powe

✍ Hassan, H.; Anis, M.; Elmasry, M. 📂 Article 📅 2008 🏛 IEEE 🌐 English ⚖ 560 KB

Low Power Pipelined Dwt-Idwt Architectur

✍ Veena M.B; M.N. Shanmukha Swamy 📂 Article 📅 2012 🏛 Elsevier 🌐 English ⚖ 441 KB

Low-power FPGA using partially low swing

✍ Yohei Matsumoto; Akira Masaki 📂 Article 📅 2005 🏛 John Wiley and Sons 🌐 English ⚖ 319 KB

LOPASS: A Low-Power Architectural Synthe

✍ Deming Chen; Cong, J.; Yiping Fan; Lu Wan 📂 Article 📅 2010 🏛 IEEE 🌐 English ⚖ 594 KB