✦ LIBER ✦

Design of a high performance memory using a novel architecture of double bit CAM and SRAM

✍ Scribed by Kayal, D.; Dandapat, A.; Sarkar, C.K.

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

Design and Performance Evaluation of a N

✍ Zhu, Y.; Kim, M. C.; Lee, K. W.; Park, Y. O.; Kuhlman, M. R. 📂 Article 📅 2001 🏛 Taylor and Francis Group 🌐 English ⚖ 238 KB

R65-45 A 105-Bit High-Speed Ferrite Memo

✍ Meier, D.A. 📂 Article 📅 1965 🏛 Institute of Electrical and Electronics Engineers 🌐 English ⚖ 256 KB

Design of High Performance 8 bit Multipl

✍ D. Kayal, P. Mostafa, A. Dandapat, C. K. Sarkar 📂 Article 📅 2013 🏛 Springer US 🌐 English ⚖ 567 KB

Design and Analysis of a Novel Adaptive

✍ Chengyu Cao; Hovakimyan, N. 📂 Article 📅 2008 🏛 IEEE 🌐 English ⚖ 383 KB

Design of a low-power, high performance,

✍ C. Senthilpari; Ajay Kumar Singh; K. Diwakar 📂 Article 📅 2008 🏛 Elsevier Science 🌐 English ⚖ 673 KB

A generalization of the single b-Bit byt

✍ Sihai Xiao; Xiaofa Shi; Guiliang Feng; Rao, T.R.N. 📂 Article 📅 1996 🏛 IEEE 🌐 English ⚖ 419 KB