Low-jitter design method based on n-doma
Low-jitter design method based on n-domain jitter analysis for 10 Gbit/s clock and data recovery ICs
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Kishine, K.; Inaba, H.; Nakamura, Ma.; Nakamura, Mi.; Ohtomo, Y.; Onodera, H.
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Article
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2009
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The Institution of Electrical Engineers
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English
β 180 KB