Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits: 2nd Edition

✍ Scribed by Manoj Sachdev, José Pineda de Gyvez (auth.), Manoj Sachdev, José Pineda de Gyvez (eds.)

Publisher: Springer US
Year: 2007
Tongue: English
Leaves: 342
Series: Frontiers in Electronic Testing 34
Edition: 2
Category: Library

No coin nor oath required. For personal study only.

✦ Synopsis

Failures of nano-metric technologies owing to defects and shrinking process tolerances give rise to significant challenges for IC testing. As the variation of fundamental parameters such as channel length, threshold voltage, thin oxide thickness and interconnect dimensions goes well beyond acceptable limits, new test methodologies and a deeper insight into the physics of defect-fault mappings are needed. In Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits state of the art of defect-oriented testing is presented from both a theoretical approach as well as from a practical point of view. Step-by-step handling of defect modeling, defect-oriented testing, yield modeling and its usage in common economics practices enables deeper understanding of concepts.

The progression developed in this book is essential to understand new test methodologies, algorithms and industrial practices. Without the insight into the physics of nano-metric technologies, it would be hard to develop system-level test strategies that yield a high IC fault coverage. Obviously, the work on defect-oriented testing presented in the book is not final, and it is an evolving field with interesting challenges imposed by the ever-changing nature of nano-metric technologies. Test and design practitioners from academia and industry will find that Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits lays the foundations for further pioneering work.

✦ Table of Contents

Introduction....Pages 1-22
Functional and Parametric Defect Models....Pages 23-67
Digital CMOS Fault Modeling....Pages 69-110
Defects in Logic Circuits and their Test Implications....Pages 111-150
Testing Defects and Parametric Variations in RAMs....Pages 151-223
Defect-Oriented Analog Testing....Pages 225-287
Yield Engineering....Pages 289-315
Conclusion....Pages 317-324

✦ Subjects

Circuits and Systems; Electronic and Computer Engineering; Engineering Design; Electronics and Microelectronics, Instrumentation

📜 SIMILAR VOLUMES

Defect-Oriented Testing for Nano-Metric

📁 Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits

✍ Manoj Sachdev, José Pineda de Gyvez 📂 Library 📅 2007 🏛 Springer 🌐 English

<p>The 2<sup>nd</sup> edition of defect oriented testing has been extensively updated. New chapters on Functional, Parametric Defect Models and Inductive fault Analysis and Yield Engineering have been added to provide a link between defect sources and yield. The chapter on RAM testing has been updat

Defect-Oriented Testing for Nano-Metric

📁 Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits

✍ Jose Nazario 📂 Library 📅 2007 🏛 Springer 🌐 English

<P>Failures of nano-metric technologies owing to defects and shrinking process tolerances give rise to significant challenges for IC testing. As the variation of fundamental parameters such as channel length, threshold voltage, thin oxide thickness and interconnect dimensions goes well beyond accept

Defect Oriented Testing for CMOS Analog

📁 Defect Oriented Testing for CMOS Analog and Digital Circuits

✍ Manoj Sachdev (auth.) 📂 Library 📅 1999 🏛 Springer US 🌐 English

Circuit Design for CMOS VLSI

📁 Circuit Design for CMOS VLSI

✍ John P. Uyemura (auth.) 📂 Library 📅 1992 🏛 Springer US 🌐 English

<p>During the last decade, CMOS has become increasingly attractive as a basic integrated circuit technology due to its low power (at moderate frequencies), good scalability, and rail-to-rail operation. There are now a variety of CMOS circuit styles, some based on static complementary con ductance p

Nanoscale CMOS VLSI Circuits: Design for

📁 Nanoscale CMOS VLSI Circuits: Design for Manufacturability

✍ Sandip Kundu, Aswin Sreedhar 📂 Library 📅 2010 🏛 McGraw-Hill Professional 🌐 English

<h4>Cutting-Edge CMOS VLSI Design for Manufacturability Techniques</h4> <p>This detailed guide offers proven methods for optimizing circuit designs to increase the yield, reliability, and manufacturability of products and mitigate defects and failure. Covering the latest devices, technologies, and p

Delay Fault Testing for VLSI Circuits

📁 Delay Fault Testing for VLSI Circuits

✍ Angela Krstić, Kwang-Ting Cheng (auth.) 📂 Library 📅 1998 🏛 Springer US 🌐 English

<p>In the early days of digital design, we were concerned with the logical correctness of circuits. We knew that if we slowed down the clock signal sufficiently, the circuit would function correctly. With improvements in the semiconductor process technology, our expectations on speed have soared. A