๐”– Scriptorium
โœฆ   LIBER   โœฆ

๐Ÿ“

Defect Oriented Testing for CMOS Analog and Digital Circuits

โœ Scribed by Manoj Sachdev (auth.)


Publisher
Springer US
Year
1999
Tongue
English
Leaves
317
Series
Frontiers in Electronic Testing 10
Category
Library

โฌ‡  Acquire This Volume

No coin nor oath required. For personal study only.

โœฆ Table of Contents


Front Matter....Pages i-xiv
Introduction....Pages 1-14
Digital CMOS Fault Modeling and Inductive Fault Analysis....Pages 15-63
Defects in Logic Circuits and Their Test Implications....Pages 65-94
Testing Defects in Sequential Circuits....Pages 95-132
Defect Oriented RAM Testing and Current Testable RAMs....Pages 133-204
Testing Defects in Programmable Logic Circuits....Pages 205-241
Defect Oriented Analog Testing....Pages 243-296
Conclusion....Pages 297-303
Back Matter....Pages 305-308

โœฆ Subjects


Electrical Engineering; Engineering Design


๐Ÿ“œ SIMILAR VOLUMES


Defect-Oriented Testing for Nano-Metric
โœ Manoj Sachdev, Josรฉ Pineda de Gyvez ๐Ÿ“‚ Library ๐Ÿ“… 2007 ๐Ÿ› Springer ๐ŸŒ English

<p>The 2<sup>nd</sup> edition of defect oriented testing has been extensively updated. New chapters on Functional, Parametric Defect Models and Inductive fault Analysis and Yield Engineering have been added to provide a link between defect sources and yield. The chapter on RAM testing has been updat

Defect-Oriented Testing for Nano-Metric
โœ Jose Nazario ๐Ÿ“‚ Library ๐Ÿ“… 2007 ๐Ÿ› Springer ๐ŸŒ English

<P>Failures of nano-metric technologies owing to defects and shrinking process tolerances give rise to significant challenges for IC testing. As the variation of fundamental parameters such as channel length, threshold voltage, thin oxide thickness and interconnect dimensions goes well beyond accept

Defect-Oriented Testing for Nano-Metric
โœ Manoj Sachdev, Josรฉ Pineda de Gyvez (auth.), Manoj Sachdev, Josรฉ Pineda de Gyvez ๐Ÿ“‚ Library ๐Ÿ“… 2007 ๐Ÿ› Springer US ๐ŸŒ English

<p><P>Failures of nano-metric technologies owing to defects and shrinking process tolerances give rise to significant challenges for IC testing. As the variation of fundamental parameters such as channel length, threshold voltage, thin oxide thickness and interconnect dimensions goes well beyond acc

Testing for Small-Delay Defects in Nanos
โœ Sandeep K. Goel, Krishnendu Chakrabarty ๐Ÿ“‚ Library ๐Ÿ“… 2013 ๐Ÿ› CRC Press ๐ŸŒ English

<P>Advances in design methods and process technologies have resulted in a continuous increase in the complexity of integrated circuits (ICs). However, the increased complexity and nanometer-size features of modern ICs make them susceptible to manufacturing defects, as well as performance and quality

Digitally-Assisted Analog and RF CMOS Ci
โœ Shouhei Kousai (auth.), Kenichi Okada, Shouhei Kousai (eds.) ๐Ÿ“‚ Library ๐Ÿ“… 2011 ๐Ÿ› Springer-Verlag New York ๐ŸŒ English

<p><p>This book describes the state-of-the-art in RF, analog, and mixed-signal circuit design for Software Defined Radio (SDR). It synthesizes for analog/RF circuit designers the most important general design approaches to take advantage of the most recent CMOS technology, which can integrate millio

Digitally-Assisted Analog and RF CMOS Ci
โœ Shouhei Kousai (auth.), Kenichi Okada, Shouhei Kousai (eds.) ๐Ÿ“‚ Library ๐Ÿ“… 2011 ๐Ÿ› Springer-Verlag New York ๐ŸŒ English

<p><p>This book describes the state-of-the-art in RF, analog, and mixed-signal circuit design for Software Defined Radio (SDR). It synthesizes for analog/RF circuit designers the most important general design approaches to take advantage of the most recent CMOS technology, which can integrate millio