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Deep sub-micron chip development

โœ Scribed by Hirokazu Ikeda

Book ID
103856053
Publisher
Elsevier Science
Year
2006
Tongue
English
Weight
171 KB
Volume
569
Category
Article
ISSN
0168-9002

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๐Ÿ“œ SIMILAR VOLUMES

Standby supply voltage minimization for
Standby supply voltage minimization for deep sub-micron SRAM
โœ Huifang Qin; Yu Cao; Dejan Markovic; Andrei Vladimirescu; Jan Rabaey ๐Ÿ“‚ Article ๐Ÿ“… 2005 ๐Ÿ› Elsevier Science ๐ŸŒ English โš– 418 KB

Suppressing the leakage current in memories is critical in low-power design. By reducing the standby supply voltage (V DD ) to its limit, which is the data retention voltage (DRV), leakage power can be substantially reduced. This paper models the DRV of a standard low leakage SRAM module as a functi

Deep sub-micron FD-SOI for front-end app
Deep sub-micron FD-SOI for front-end application
โœ H. Ikeda; Y. Arai; K. Hara; H. Hayakawa; K. Hirose; Y. Ikegami; H. Ishino; Y. Ka ๐Ÿ“‚ Article ๐Ÿ“… 2007 ๐Ÿ› Elsevier Science ๐ŸŒ English โš– 213 KB

In order to confirm benefits of a deep sub-micron FD-SOI and to identify possible issues concerning front-end circuits with the FD-SOI, we have submitted a small design to Oki Electric Industry Co., Ltd. via the multi-chip project service of VDEC, the University of Tokyo. The initial test results an