Standby supply voltage minimization for deep sub-micron SRAM

✍ Scribed by Huifang Qin; Yu Cao; Dejan Markovic; Andrei Vladimirescu; Jan Rabaey

• Book ID: 104051025
• Publisher: Elsevier Science
• Year: 2005
• Tongue: English
• Weight: 418 KB
• Volume: 36
• Category: Article
• ISSN: 0026-2692
• DOI: 10.1016/j.mejo.2005.03.003

✦ Synopsis

Suppressing the leakage current in memories is critical in low-power design. By reducing the standby supply voltage (V DD ) to its limit, which is the data retention voltage (DRV), leakage power can be substantially reduced. This paper models the DRV of a standard low leakage SRAM module as a function of process and design parameters, and analyzes the SRAM cell stability when V DD approaches DRV. The DRV model is verified using simulations as well as measurements from a 4 KB SRAM chip in a 0.13 mm technology. Due to a large on-chip variation, DRV of the 4 KB SRAM module ranges between 60 and 390 mV. Measurements taken at 100 mV above the worst-case DRV show that reducing the SRAM standby V DD to a safe level of 490 mV saves 85% leakage power. Further savings can be achieved by applying DRVaware SRAM optimization techniques, which are discussed at the end of this paper.