Cross-Talk Noise Immune VLSI Design Using Regular Layout Fabrics
β Scribed by Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli (auth.)
- Publisher
- Springer US
- Year
- 2001
- Tongue
- English
- Leaves
- 122
- Edition
- 1
- Category
- Library
No coin nor oath required. For personal study only.
β¦ Synopsis
This book was motivated by the problems being faced with shrinking IC process feature sizes. It is well known that as process feature sizes shrink, a host of electrical problems like cross-talk, electromigration, self-heat, etc. are becoming important. Cross-talk is one of the major problems since it results in unpredictable design behavior. In particular, it can result in significant delay variation or signal integrity problems in a wire, depending on the state of its neighboring wires. Typical approaches to tackle the cross-talk problem attempt to fix the problem once it is created. In our approach, we ensure that cross-talk is eliminated by design. The work described in this book attempts to take an "outside-the-box" view and propose a radically different design style. This design style first imposes a fixed layout pattern (or fabric) on the integrated circuit, and then embeds the circuit being implemented into this fabric. The fabric is chosen carefully in order to eliminate the cross-talk problem being faced in modem IC processes. With our choice of fabric, cross-talk between adjacent wires on an IC is reduced by between one and two orders of magnitude. In this way, the fabric concept eliminates cross-talk up-front, and by design. We propose two separate design flows, each of which uses the fabric concept to implement logic. The first flow uses fabric-compliant standard cells as an imΒ plementation vehicle. We call these cells fabric cells, and they have the same logic functionality as existing standard cells with which they are compared.
β¦ Table of Contents
Front Matter....Pages i-xix
Introduction....Pages 1-5
Validating Deep Sub-Micron Effects....Pages 7-21
VLSI Layout Fabrics....Pages 23-37
Fabric1 β Fabric Cell Based Design....Pages 39-51
Fabric3 β Network of PLA Based Design....Pages 53-77
Wire Removal in a Network of Plas....Pages 79-94
Conclusions and Future Directions....Pages 95-102
Back Matter....Pages 103-112
β¦ Subjects
Circuits and Systems; Electrical Engineering; Computer-Aided Engineering (CAD, CAE) and Design
π SIMILAR VOLUMES
<p>Introduction The exponential scaling of feature sizes in semiconductor technologies has side-effects on layout optimization, related to effects such as interΒ connect delay, noise and crosstalk, signal integrity, parasitics effects, and power dissipation, that invalidate the assumptions that form
Regular Fabrics in Deep Sub-Micron Integrated-Circuit Design discusses new approaches to better timing-closure and manufacturability of DSM Integrated Circuits. The key idea presented is the use of regular circuit and interconnect structures such that area/delay can be predicted with high accuracy.