✦ LIBER ✦

Constrained algorithmic IP design for system-on-chip

✍ Scribed by P. Coussy; E. Casseau; P. Bomel; A. Baganne; E. Martin

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

IP protection of DSP algorithms for syst

✍ Chapman, R.; Durrani, T.S. 📂 Article 📅 2000 🏛 IEEE 🌐 English ⚖ 170 KB

Integration and verification case of IP-

✍ Yue-li Hu; Chen Zhou 📂 Article 📅 2010 🏛 Chinese Electronic Periodical Services 🌐 English ⚖ 737 KB

System Level Design for System on a Chip

✍ W. Shields Neely; Vincent John Mooney 📂 Article 📅 1998 🏛 Springer US 🌐 English ⚖ 86 KB

Asynchronous Techniques for System-on-Ch

✍ Martin, A.J.; Nystrom, M. 📂 Article 📅 2006 🏛 IEEE 🌐 English ⚖ 588 KB

Reliable network-on-chip design for mult

✍ Kuei-Chung Chang 📂 Article 📅 2009 🏛 Springer US 🌐 English ⚖ 958 KB

Reliable network-on-chip design for mult

✍ Kuei-Chung Chang 📂 Article 📅 2009 🏛 Springer US 🌐 English ⚖ 958 KB