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Computing optimal test sequences from complete test sets for stuck-open faults in CMOS circuits

โœ Scribed by Chakravarty, S.; Ravi, S.S.


Book ID
119778020
Publisher
IEEE
Year
1990
Tongue
English
Weight
354 KB
Volume
9
Category
Article
ISSN
0278-0070

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โœ Leonard J. Tung; David V. Kerns ๐Ÿ“‚ Article ๐Ÿ“… 1988 ๐Ÿ› Elsevier Science ๐ŸŒ English โš– 581 KB

A new algorithm to generate test sets for stuck-at faults in combinational logic circuits via fault simulation is presented. The algorithm is non-path-sensitizing, non-pathtracing and can be easily implemented on a computer. The stuck-at fault model in the algorithm is developed using the component