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Computer-Aided Test Generation for Four-Phase MOS LSI Circuits

โœ Scribed by Yao Tung Yen


Book ID
114587464
Publisher
IEEE
Year
1969
Tongue
English
Weight
876 KB
Volume
C-18
Category
Article
ISSN
0018-9340

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[IEEE Comput. Soc. Press 1993 Internatio
โœ Upadhyaya, S.J.; Chen, L.-C. ๐Ÿ“‚ Article ๐Ÿ“… 1993 ๐Ÿ› IEEE Comput. Soc. Press โš– 464 KB

A new on-chip test generation technique based on the built-in self test (BIST) and deterministic test generation concepts has been proposed. Given a test set, the test patterns can be regenerated on the chip and applied to the circuit under test without the use of any external test equipments.A syst