Combining technology mapping and placement for delay-minimization in FPGA designs

✍ Scribed by Chau-Shen Chen; Yu-Wen Tsay; TingTing Hwang; Wu, A.C.H.; Youn-Long Lin

• Book ID: 119777975
• Publisher: IEEE
• Year: 1995
• Tongue: English
• Weight: 911 KB
• Volume: 14
• Category: Article
• ISSN: 0278-0070
• DOI: 10.1109/43.406709