Built-in current testing for CMOS logic circuits using random patterns

✍ Scribed by Hiroshi Yokoyama; Hideo Tamamoto; Yuichi Narita

• Publisher: John Wiley and Sons
• Year: 1994
• Tongue: English
• Weight: 829 KB
• Volume: 25
• Category: Article
• ISSN: 0882-1666
• DOI: 10.1002/scj.4690251101

✦ Synopsis

Abstract

With respect to CMOS logic circuits, it is reported that a fault can occur cannot be covered by conventional classical fault model, and the current testing is considered to be interesting as a testing method to detect such a fault.

This paper proposes a fault‐detection method for the CMOS logic circuit which can detect the stuck‐at fault and the stuck‐open fault based on the dynamic power supply current observed when a pseudorandom pattern is applied as the input. A built‐in testing circuit for realizing the principle is shown. The feature of the current testing is that the fault can be detected by observing the power supply current as long as the fault in the circuit is activated, and it is not required to propagate the fault information to the output. Based on that property, a random pattern with a small test generation cost is used as the test pattern.

As the test pattern, the pseudorandom pattern is generated autonomously by utilizing the output signal of the circuit under test. The fault detection is made easier by this pattern generation since the effect of the fault on the power supply current is enhanced. In determining whether or not the power supply current is that of the normal circuit, a method based on the time‐course of the power supply current is used, with the power supply currents for various test patterns as the feature parameter. The proposed procedure is evaluated by a simulation, and the usefulness of the proposed method is demonstrated.