Abstract
As a technique for complementing the long testing time, which is a shortcoming of pseudo‐random pattern test, we will propose a BIST‐oriented test pattern generator (TPG) which achieves high fault detection efficiency with a short testing time for transition faults. The proposed TPG is composed by adding LFSR, shift registers, and multiplexers to the scan part. The partial sequences of ATPG vectors are stored in an on‐chip RDM or external tester and the scan‐in is performed. The test patterns are generated, which are the result of mixing the partial sequence of ATPG vectors and the pseudo‐random vectors generated by LFSR. Since the random pattern resistant faults will be detected by the partial sequences of ATPG vectors, a high fault detection efficiency can be achieved with a short testing time. Since it is not necessary to perform the scan‐in for every operation clock, the real operation speed test using a low‐speed tester is possible. We will also show a technique for reducing the ATPG vectors to be stored. The proposed technique is evaluated, by using ISCAS benchmark circuits, for testing time, fault detection efficiency, and hardware quantity, and the effectiveness of the proposed technique is examined. © 2003 Wiley Periodicals, Inc. Syst Comp Jpn, 34(3): 76–84, 2003; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/scj.1196