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Analysis of the robustness of the TMR architecture in SRAM-based FPGAs

✍ Scribed by Sterpone, L.; Violante, M.

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

A New Algorithm for the Analysis of the

✍ Sterpone, Luca; Violante, Massimo 📂 Article 📅 2008 🏛 IEEE 🌐 English ⚖ 694 KB

A new analytical approach to estimate th

✍ Sterpone, L.; Violante, M. 📂 Article 📅 2005 🏛 IEEE 🌐 English ⚖ 178 KB

Effectiveness of TMR-Based Techniques to

✍ Manuzzato, Andrea; Gerardin, Simone; Paccagnella, Alessandro; Sterpone, Luca; Vi 📂 Article 📅 2008 🏛 IEEE 🌐 English ⚖ 445 KB

Reliability Limits of TMR Implemented in

✍ Gilles Foucard; Paul Peronnard; Raoul Velazco 📂 Article 📅 2011 🏛 Springer US 🌐 English ⚖ 280 KB

An Efficient BIST Architecture for Delay

✍ Patrick Girard; Olivier Héron; Serge Pravossoudovitch; Michel Renovell 📂 Article 📅 2006 🏛 Springer US 🌐 English ⚖ 855 KB

Soft Error Susceptibility Analysis of SR

✍ Asadi, Hossein; Tahoori, Mehdi B.; Mullins, Brian; Kaeli, David; Granlund, Kevin 📂 Article 📅 2007 🏛 IEEE 🌐 English ⚖ 447 KB